An ADC is an electronic circuit that converts a continuous analog signal, such as a voltage signal, to a discrete digital number. Due to the popularity of consumer electronic devices, there are a large number of applications that employ ADCs with medium resolution, such as 10 bits, and medium to high data rates ranging from a few MHz to several tens of MHz. Among these applications are wireless communication systems, mobile phones, video components, imaging components, local area network transceivers, and the like.
Pipelined ADCs have multiple stages which successively process an analog input signal. The principal in pipelined ADCs is to find a set of reference voltages whose sum equals the signal sample being converted. This is realized by subtracting different reference voltages from the input sample until the residue value becomes zero, indicating that the sum of the subtracted references equals the original signal sample. In the pipeline, the analog residue or remainder value may be amplified by an amplifier between the subtraction steps in order to increase accuracy prior to being fed to the next stage in the pipeline.
FIG. 1 is a high-level block diagram of a conventional 10-bit pipelined ADC. There are two basic types of components within the ADC: 1) pure analog components which include a reference voltage generator, a bias current generator, a track and hold (T&H) stage, front end pipeline stages (1 through 4) and back end pipeline stages (5 through 8); and 2) digital and mixed analog/digital components including a phases generator, a 2 bit ADC flash unit, delay lines, and a Redundant Signed Digital (RSD) error correction unit.
In the pipelined architecture shown in FIG. 1, the ADC has nine stages which process the analog input signal. However, the number of stages in a pipelined architecture can be any number depending on the desired resolution of the ADC. The greater the number of stages in an ADC the higher the resolution. From the left side of FIG. 1, the analog input signal first enters the (T&H) stage. Subsequent pipeline stages 1 through 8 process the T&H output and drive a 2 bit ADC on the right. In each of the nine stages, an operational transconductive amplifier (OTA) is the active consuming analog cell. As an example, the ADC shown in FIG. 1 uses an external s-bits bus (speed<s-1:0>), where s may be any number, in order to program the ADC with a specific amount of active current that is proportional to the targeted data rate of the ADC.
Referring to FIG. 2, a block diagram of a single pipeline stage is shown. The single pipeline stage includes a sample and hold (S/H) unit for providing a constant analog signal, an ADC, a digital-to-analog converter (DAC), a summer and an OTA. The input Vj is the sample number j coming out from the previous pipeline stage as a new input to the present stage. It is sampled and held, and also quantized with a low resolution 2 bit ADC. The resulting digital word Dj<1:0> is converted back to analog using a 2 bit DAC and subtracted from the original held value to create a residue. The residue is then amplified by Gj to generate an output voltage Vj+1 to the next pipeline stage given by Equation (1) as follows:Vj+1=Gj·(Vj−VjDA(Dj)).  Equation (1)
When considering the switched capacitor implementation, the S/H function as well as the DAC, the voltage subtraction and the residue amplification may be performed by a single operation known by those skilled in the art as a multiplying DAC or MDAC. The MDAC performs the operation in a period that is set by half a clock period, due to the switched capacitor circuit implementation. During a first half clock period the sample value is stored in a first capacitor. During a second half clock period the sample value is amplified by an OTA and multiplied by a gain value.
Since the 2 bit ADC-DAC implementation has a very low resolution, it is designed to provide a very high speed response. A limiting element of the pipeline stage, in terms of speed, is the OTA, which performs and provides the Vj+1 output. Setting the gain Gj with a high enough resolution not to degrade the final ADC converter resolution, results in high power consumption. Additionally, the overall speed of the OTA is directly dependent upon the power consumption. The more power that is provided to the OTA, the faster the speed of the OTA and the conversion data rate of the ADC device. However, the increased speed of the OTA results in higher power consumption of the ADC. This is a significant drawback, particularly for wireless devices and other consumer electronic devices which rely upon a battery as a power source.
Accordingly, what is needed is a versatile pipelined ADC which can operate at a desired resolution over a wide operating range without the drawback of high power consumption of current pipelined ADCs. Moreover, an ADC that is independent of circuit process variations for providing a reliable resolution is desirable.